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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Shift Register with Output Storage Register
(3-State)
The MC74VHC595 is an advanced high speed 8-bit shift register with an output storage register fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC595 contains an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going transition of the Shift Clock input (SCK). The output register is loaded with the contents of the shift register on the positive going transition of the Register Clock input (RCK). Since the RCK and SCK signals are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3-state, the VHC595 can be directly connected to an 8-bit bus. This register can be used in serial-to-parallel conversion, data receivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. * * * * * * * * * * * High Speed: fmax = 185MHz (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 1.0V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 328 FETs or 82 Equivalent Gates
MC74VHC595
D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05
DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01
M SUFFIX 16-LEAD SOIC EIAJ PACKAGE CASE 966-01 ORDERING INFORMATION MC74VHCXXXD MC74VHCXXXDT MC74VHCXXXM SOIC TSSOP SOIC EIAJ
PIN ASSIGNMENT
QB QC QD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA SI OE RCK SCK SCLR SQH
LOGIC DIAGRAM
SERIAL DATA INPUT 14 15 1 2 3 SHIFT REGISTER STORAGE REGISTER 4 5 6 7 11 10 12 13 9 SQH SERIAL DATA OUTPUT
QE QF QA QB QC QD QE QF QG QH PARALLEL DATA OUTPUTS QG QH GND
SI
SCK SCLR RCK OE
6/97
(c) Motorola, Inc. 1997
1
REV 1
MC74VHC595
FUNCTION TABLE
Inputs Reset (SCLR) L H H H X X X Serial Input (SI) X D X X X X X Shift Clock (SCK) X L, H, L, H, X X X Reg Clock (RCK) L, H, L, H, X L, H, X X Output Enable (OE) L L L L L L H = High-to-Low = Low-to-High Shift Register Contents L DSRA; SRNSRN+1 U U * * * SRN Resulting Function Storage Register Contents U U ** Serial Output (SQH) L SRGSRH U * * * * Parallel Outputs (QA - QH) U U ** SRN U Enabled Z
Operation O i Clear shift register Shift data into shift register Registers remains unchanged Transfer shift register contents to storage register Storage register remains unachanged Enable parallel outputs Force outputs into high impedance state
STRN
U ** **
SR = shift register contents D = data (L, H) logic level STR = storage register contents U = remains unchanged
* = depends on Reset and Shift Clock inputs ** = depends on Register Clock input
IIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I IIIIIIII I IIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to + 7.0 Vout IIK DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW Tstg - 65 to + 150
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
v
v
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
III I I I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
Symbol VCC Vin Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage Vout TA DC Output Voltage VCC + 85 100 20 Operating Temperature, All Package Types Input Rise and Fall Time - 40 0 0
_C
tr, tf
VCC = 3.3V 0.3V VCC =5.0V 0.5V
ns/V
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I II II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) DC ELECTRICAL CHARACTERISTICS
Symbol S bl S bl Symbol tPLH, tPHL tPLH, tPHL tPZL, tPZH tPHL VOH fmax VOL ICC IOZ VIH VIL Iin Output Enable Time, OE to QA - QH Propagation Delay, RCK to QA - QH Propagation Delay, SCLR to SQH Propagation Delay, SCK to SQH Maximum Clock Frequency (50% Duty Cycle) Maximum Quiescent Supply Current Maximum Input Leakage Current Three-State Output Off-State Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage P Parameter Parameter P Vin = VCC or GND Vin = 5.5V or GND Vin = VIH or VIL Vout = VCC or GND Vin = VIH or VIL IOL = 4mA IOL = 8mA Vin = VIH or VIL IOL = 50A Vin = VIH or VIL IOH = - 4mA IOH = - 8mA Vin = VIH or VIL IOH = - 50A T Test C di i Conditions VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k Test C di i T Conditions 0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 to 5.5 VCC V 5.5 5.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 1.50 VCC x 0.7 2.58 3.94 Min 1.9 2.9 4.4 Min 135 95 80 55 TA = 25C Typ 0.0 0.0 0.0 2.0 3.0 4.5 TA = 25C 7.7 10.2 8.4 10.9 8.8 11.3 Typ 185 155 150 130 4.8 8.3 7.5 9.0 5.4 6.9 5.9 7.4 6.2 7.7 0.50 VCC x 0.3 0.25 0.1 0.36 0.36 Max 4.0 0.1 0.1 0.1 12.8 16.3 13.0 16.5 Max 11.5 15.0 11.9 15.4 8.6 10.6 8.0 10.0 8.2 10.2 7.4 9.4 1.50 VCC x 0.7 TA = - 40 to 85C 2.48 3.80 Min 1.9 2.9 4.4 TA = - 40 to 85C Min 115 85 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 70 50
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
3
MC74VHC595
0.50 VCC x 0.3
2.50
1.0
40.0
0.44 0.44
Max
0.1 0.1 0.1
10.0 12.0
13.5 17.0
13.5 17.0
13.7 17.2
15.0 18.5
Max
8.5 10.5
9.1 11.1
9.4 11.4
MOTOROLA MHz Unit Ui Ui Unit A A A ns ns ns ns V V V V
II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol S bl tsu(H) VOLP VOLV tsu(L) VIHD tw(L) VILD th(L) trec tsu tw th Maximum Low Level Dynamic Input Voltage Minimum High Level Dynamic Input Voltage Quiet Output Minimum Dynamic VOL Quiet Output Maximum Dynamic VOL Pulse Width, SCLR Pulse Width, SCK or RCK Recovery Time, SCLR to SCK Hold Time, SCLR to RCK Hold Time, SI to SCK Setup Time, SCLR to RCK Setup Time, SCK to RCK Setup Time, SI to SCK Parameter P VCC V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Typ TA = 25_C Limit - 0.8 5.0 5.0 5.0 5.0 3.0 2.5 1.5 2.0 8.0 5.0 8.0 5.0 3.5 3.0 0.8 0 0 TA = - 40 to 85C Limit - 1.0 5.0 5.0 5.0 5.0 3.0 2.5 1.5 2.0 9.0 5.0 8.5 5.0 3.5 3.0 1.5 3.5 1.0 0 0 Unit Ui ns ns ns ns ns ns ns ns V V V V
II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I II I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MC74VHC595
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol tPLZ, tPHZ Cout Cin Three-State Output Capacitance (Output in High- Impedance State), QA - QH Input Capacitance Output Disable Time, OE to QA - QH Parameter VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k Test Conditions CL = 50pF CL = 50pF Min TA = 25C 12.1 Typ 7.6 6 4 Typical @ 25C, VCC = 5.0V Max 10.3 15.7 10 TA = - 40 to 85C Min 1.0 1.0 16.2 Max 11.0 10 10 Unit pF ns
CPD Power Dissipation C P Di i i Capacitance (N i (Note 1 ) 1.) pF F 87 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
MOTOROLA Symbol S bl Characteristic Ch ii
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 1 Typ TA = 25C Max Unit Ui
MC74VHC595
SWITCHING WAVEFORMS
tw VCC SCK 50% tw 1/fmax tPLH SQH 50% VCC tPHL GND VCC SCLR tPHL SQH 50% VCC trec VCC SCK 50% GND 50% GND
Figure 1.
Figure 2.
VCC RCK 50% VCC GND tPLH QA-QH 50% VCC QA-QH tPHL OE 50% GND tPZL QA-QH 50% VCC tPZH 50% VCC tPHZ tPLZ HIGH IMPEDANCE VOL +0.3V VOH -0.3V HIGH IMPEDANCE
Figure 3.
VCC SCLR 50% VALID SI 50% GND tsu SCK or RCK th 50% VCC GND RCK GND VCC SCK
Figure 4.
VCC 50% GND tsu(H) 50% GND tw VCC
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 7.
Figure 8.
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
MOTOROLA
MC74VHC595
EXPANDED LOGIC DIAGRAM
13
OE
RCK
12
SI
14
D SRA R D SRB R D SRC R D SRD R D SRE R D SRF R D SRG R D
Q
D STRA
Q
15
QA
Q
D STRB
Q
1
QB
Q
D STRC
Q
2
QC
Q
D STRD
Q
3
QD PARALLEL DATA OUTPUTS
Q
D STRE
Q
4
QE
Q
D STRF
Q
5
QF
Q
D STRG
Q
6
QG
Q SRH
D STRH
Q
7
QH
SCK
11 R 10
SCLR
9
SQH
MOTOROLA
6
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC595
TIMING DIAGRAM
SCK SI SCLR RCK OE
QA QB QC QD QE QF QG QH SQH NOTE: output is in a high-impedance state.
INPUT EQUIVALENT CIRCUIT
INPUT
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
7
MOTOROLA
MC74VHC595
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
MOTOROLA
8
EE CC EE CC
-W-
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHC595
OUTLINE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78
INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
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VHC Data - Advanced CMOS Logic DL203 -- Rev 1
9
MC74VHC595/D MOTOROLA

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